There are many commercially successful non-volatile memory products being used today, particularly in the form of small cards, which use an array of flash EEPROM cells. The basic architecture of an individual EEPROM memory cell includes source and drain diffusions, coupled by a channel, formed in a semiconducting substrate. The charge storage unit itself is positioned above the channel, separated from it by a dielectric layer. This charge storage unit is often referred to as a floating gate. Overlying the charge storage unit there can be a control gate, used to address the individual cell for programming and reading.
Some designs include a split channel architecture, as described, for example, in U.S. Pat. No. 5,095,344, granted to E. Harari, which is incorporated herein by this reference in its entirety. In a split channel cell both the charge storage unit and the control gate partially overlie the channel. This design has the advantage of simplicity, but the control gate performs the multiple functions of addressing the individual cells to be programmed or read, as well as the function of participating in the actual programming or reading of the cells.
Another design introduces an additional gate structure. This additional gate partially overlies the channel region and partially overlies the control gate. The portion that overlies the channel region forms a transistor that performs a selecting function. Therefore, this is generally called the select gate. The control gate is often called a “steering gate” in this arrangement. The select gate to carries out the addressing function and even may contribute to the programming, but the primary programming and reading functions are performed by the steering gate, as described, for example, in U.S. Pat. No. 5,313,421, granted to D. Guterman et al., which is incorporated herein by this reference in its entirety. This kind of memory cell is illustrated schematically in FIG. 1(a). The corresponding device structure is shown in FIG. 1(b).
Higher storage densities can be achieved by a dual cell design, as described, for example, in U.S. Pat. No. 5,712,180, granted to D. Guterman et al., which is incorporated herein by this reference in its entirety. There are two floating gates per cell in the dual cell architecture, overlying portions of the same channel. Corresponding steering gates are positioned above the floating gates. The select gate is formed above the steering gates and also overlies the channel itself. This type of memory cell is illustrated schematically in FIG. 2(a). The corresponding device structure is shown in FIG. 2(b).
In an array of cells the select gates of the memory cells along a row are usually coupled to form a wordline along that row. The diffusions in different rows are aligned and coupled to form bitlines that run along columns. Also, the steering gates in different rows are aligned and coupled to form steering lines that run along columns. A recent design of a memory cell array is described in U.S. Pat. No. 6,151,248, granted to E. Harari, which is incorporated herein by this reference in its entirety.
An alternative architecture is described in U.S. Pat. No. 6,091,633 granted to Cernea. Steering gates are connected along rows to form wordlines and select gates are connected together along columns to form bit selection lines. This is the reverse of the conventional arrangement. The diffusions in different rows are aligned and coupled to form bitlines that run along columns as in the conventional arrangement. This array architecture has certain advantages over conventional arrangements. The advantages of this arrangement as applied to embodiments of the present invention are further described in the description section.
Typically, each floating gate holds one bit of information. That is, the floating gate is either charged or not, representing a one or a zero. Alternatively, higher storage density may be achieved by using a range of charge levels to represent a range of memory states. Such a system is described in patent application Ser. No. 09/793,370 (publication number 20020118574) by Gongwer, filed on Feb. 26, 2001.
Flash EEPROM memories hold some key advantages over other types of memory systems. One of these advantages is the non-volatile nature of the data storage, making these systems prime candidates for a wide variety of applications, including digital cameras, recording music and utilization in mobile communications. Flash EEPROM is frequently used in memory cards that can be inserted or removed from such devices while maintaining the data stored in the memory.
A characteristic of flash memory systems is, however, the relatively long time it takes to program the cells. Programming can take as long as 10–1000 microseconds, longer than, for example, present day DRAMs.
Many cells are programmed simultaneously in the memory systems. The cells of the array are selected for programming in a certain scheme. The speed of the programming is influenced by this scheme. In some arrays the simultaneous programming is performed, for example, on every fourth, or every seventh cell only. Therefore these schemes require four or seven programming cycles to program all the cells of the array, respectively. One approach to increasing the speed of programming is to program adjacent cells at the same time. This is described, for example, in U.S. Pat. No. 6,493,269 by Cernea, which is incorporated herein by this reference in its entirety. However, the individual programming cycles may still be time consuming even if the number of cycles is reduced.
Thus, programming schemes that program memory arrays more rapidly than conventional schemes are desired.
Conventional techniques for programming memory cells use programming steps followed by verification steps to achieve the required memory state. Several such steps may be required to program a cell in this manner. This can be time consuming. Therefore, reducing the number of verification steps, or eliminating the need for verification, is desired.